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The Silicon at Both Ends of Meta's Tether

By my arithmetic, Meta's VR Glasses panels need up to 40 Gbps uncompressed, more than the Qualcomm chip's one DisplayPort 1.4 output carries.

Evyatar Bluzer
8 min read

The launch coverage of Meta's VR Glasses described the cable and stopped there. UploadVR said it most plainly: "no onboard computing, not even a tracking coprocessor." Meta has published no bit rate for that cable, but its own panel spec is enough to derive one, and the derived number says the glasses cannot be that empty.

Part 1 of six on what Meta's and Qualcomm's Connect 2026 documents say that the keynote did not.

TL;DR

  • By my arithmetic from Meta's panel spec, the VR Glasses' display stream needs about 32 Gbps uncompressed at 8-bit color and 40 Gbps at 10-bit; the one DisplayPort 1.4 output on Qualcomm's Snapdragon Reality Elite carries 25.92 Gbps, per VESA, enough for one eye.
  • Meta researchers' saccade-contingent rendering paper simulates bit savings of 9 to 16 percent at 40 pixels per degree and calls them not significant below 35; the VR Glasses sit at 37.
  • Any optical tether ends in active silicon inside the VR Glasses, an optical transceiver at minimum, whatever UploadVR's "no onboard computing" meant.
  • My read: a rival can buy the puck's Snapdragon chip from Qualcomm, but not the link silicon at both ends of the VR Glasses tether, behind an interconnect Meta's Angela Chang called "pretty proprietary," per MobileSyrup.

What does the VR Glasses tether actually carry?

Downward, by my arithmetic from Meta's panel spec, finished frames worth up to about 40 billion bits a second before compression. Meta's developer compare page lists two 2412x2288 micro-OLED panels at 120 Hz and 37 pixels per degree: 5.52 million pixels per eye, so 5.52 million x 2 x 120 = 1.32 billion pixels a second, or 31.8 Gbps at 24 bits per pixel and 39.7 Gbps at 30, the 10-bit color Meta's HDR10 support requires. That counts active pixels only, so blanking adds to it on a real link.

Per Meta's announcement, the glasses "handle the sensors and display" and the puck, "connected by an optical tether," handles "compute, battery, and storage" on Snapdragon Reality Elite (XR2 Gen 3 on Meta's developer pages). So sensor streams ride the cable up. Qualcomm's brief sizes the chip for two 12 MP Bayer passthrough streams at 90 frames a second, 12 million x 90 = 1.08 billion pixels a second each: the chip's ceiling, not the glasses' load, since Meta's compare page gives passthrough only as 26 pixels per degree and names no camera resolution. At that ceiling and an assumed 10 bits per raw Bayer sample, one color per pixel, the pair would push 2 x 1.08 billion x 10 = 21.6 Gbps up, about two-thirds of the 8-bit stream coming down, by my arithmetic. Per UploadVR, XREAL's Aura does its computer vision in the glasses "to avoid the enormous bandwidth requirement of transmitting the camera data to the puck." If Meta's glasses carry "not even a tracking coprocessor," that bandwidth rides the fiber.

Meta VR Glasses, tether and puckPhoto of the VR Glasses floating above the compute puck, with both visible runs of the braided tether traced in the accent color; three labels in the right margin point to the glasses, the tether and the puck. Glasses: sensors and display Per Meta, about 100 grams Optical tether Down: frames; if uncompressed, about 32 Gbps at 8-bit color, 40 at 10-bit Up: tracking and passthrough sensor streams, volume unpublished Active pixels, from Meta's panel spec; Meta publishes no bit rate Puck: compute, battery, storage Per Meta, on Snapdragon Reality Elite
Meta's product image of the VR Glasses and puck with both visible runs of the optical tether traced; the duties on each side are as Meta describes them, and the 32 to 40 Gbps is my uncompressed active-pixel arithmetic from Meta's panel spec, since Meta publishes no bit rate. Photo: Meta.

One display output, two eyes

Qualcomm's product brief for Reality Elite (revision B) lists "4x DSI, 2x eDP, 1x DP1.4 over USB" and up to 4.4K x 4.4K per eye at 90 Hz, 4400 x 4400 x 2 x 90 = 3.48 billion pixels a second, 2.6 times the VR Glasses' load. VESA's Display Stream Compression (DSC) page files eDP and MIPI's DSI as embedded interfaces, links inside a device, leaving DP 1.4 over USB-C as the chip's one off-board output, and VESA puts the payload of HBR3, DP 1.4's top link rate, at 25.92 Gbps. One eye is 15.9 Gbps, or 19.9 at 10-bit; two need at least 31.8 / 25.92 = 1.23:1 compression at 8-bit and 1.53:1 at 10-bit.

Why doesn't perception shrink the link?

Because at 37 pixels per degree the eye's discount is small, and the large one, foveation, saves shading in the puck rather than bits on the wire. Saccade-Contingent Rendering (arXiv:2401.16536), from Reality Labs researchers, renders a coarser image during the short loss of acuity after each saccade, the eye's jump between fixations. Its bit savings run 9 to 16 percent at 40 pixels per degree (ppd) and about 80 at 90, and are not significant below 35. The VR Glasses sit between the paper's 30 and 40 ppd points, under the lowest figure it quotes, and even that figure leaves 31.8 x (0.84 to 0.91) = about 27 to 29 Gbps at 8-bit and about 33 to 36 at 10-bit, over the payload either way.

The bigger catch: the paper simulates one temporal effect as a proxy for power and compute, measures no link rate, and says the effect shrinks when stacked with the lever this device does have.

Savings would be reduced if other methods drop the target render resolution below thresholds from Equation 1, like in foveated rendering where spatial resolution is lowered in the periphery.

Meta's developer docs list eye-tracked foveated rendering on the VR Glasses and put fixed foveation's payoff at up to 25 percent more frame rate in pixel-intensive apps, a gain for the puck's GPU. The panels still take every native pixel unless something on the glasses upsamples a foveated frame, and nothing Meta has published describes one.

DSC at 8 bits per pixel gets either depth to 1.32 billion x 8 = about 10.6 Gbps. VESA calls the codec "visually lossless" on the strength of its members' testing, a verdict it illustrates with 8K and 4K display modes. At 37 pixels per degree a pixel spans 60 / 37 = 1.6 arcminutes, wider than the 1 arcminute a 20/20 eye resolves, so a one-pixel codec artifact is visible, and I found no published test of DSC at that angular pixel size.

Tether downlink against DisplayPort 1.4Horizontal bar chart with five bars against a vertical rule at 25.92 Gbps: the 8-bit bar at 31.8 and the 10-bit bar at 39.7 each carry a divider at one eye's share and cross the rule, with the part past the rule highlighted; thinner bars beneath each show the range after a 9 to 16 percent saving, still past the rule; a fifth bar at 10.6 for DSC stops well short of it.010203040Gbps down the tether, both eyes at 120 Hzone eye 15.9one eye 19.931.826.7-28.939.733.4-36.210.68-bit color (24 bpp)after 9-16% saccade saving10-bit color (30 bpp)after 9-16% saccade savingDSC at 8 bpp, either depthDisplayPort 1.4 payload, 25.92
Uncompressed downlink for two 2412x2288 panels at 120 Hz against the 25.92 Gbps DisplayPort 1.4 payload: one eye fits, two do not at either color depth, the saccade paper's 9-16% saving at 40 ppd still leaves both over, and DSC at 8 bpp brings either to 10.6; my arithmetic from Meta's compare page, VESA and arXiv:2401.16536.

Every branch ends in silicon on the face

The fiber's price is an optical transceiver at each end. Past the transceivers, Meta has two ways across: serialize the chip's embedded panel lanes and deserialize them on the face, or send DisplayPort with DSC and convert it for the panels there. Compression alone proves little about the face: as Rambus notes, DSC decoders already live in phone panels' driver ICs.

Time is the one other lever that shrinks this link, and it takes a warp engine on the face, a block that shifts each rendered frame to the newest head pose: send 60 frames a second, let the face synthesize the other 60, and the stream halves to one eye's worth, under one DisplayPort payload uncompressed. That is my inference; Meta has described no such engine.

Whoever owns the plug

Asked at a press roundtable MobileSyrup reported whether buyers could swap in pucks of different power levels, Angela Chang, Meta's VP of product management, said Meta "had to use a pretty proprietary interconnect on both the glasses and the puck side." The compare page also puts a DisplayPort input on the puck; Qualcomm's brief lists DisplayPort only as an output, so the receiver is link silicon beyond Qualcomm's at the pocket end too, by my inference.

So the tether is the product. The Snapdragon chip is the part anyone can buy; XREAL announced Aura on it in June, and the June call that Aura ships on Reality Elite this fall is still open. The loser is Qualcomm's pitch that Reality Elite is the platform: behind Meta's link it is a socket Meta can refill in a later puck without touching the glasses, and no PC or console maker gets to build the puck.

All-day glasses inherit the split with one amendment the numbers force: the display is what needs the wire. The chip's 5.8 Gbps Wi-Fi 7 peak is about a seventh of the 10-bit stream (5.8 / 39.7) and about half the 10.6 Gbps DSC one. Six microphones like Ray-Ban Meta Audio's, at a generous 48 kHz and 24 bits, need 6 x 48,000 x 24 = about 7 Mbps, a thousandth of that peak.

Three dated calls. Meta publishes no tether bit rate or compression scheme before the VR Glasses ship, graded June 30, 2027. No third-party puck, sold or officially supported, works with the VR Glasses before 2028. And by September 30, 2027, a published teardown finds a chip in the display path, between the optical transceiver and the panel drivers, that is neither of those: a bridge, a warp engine or a compositor, not a camera aggregator or eye-tracking ISP, because the frame-synthesis lever only works on the face. If the display path holds only the transceiver and the panels' driver ICs, the last warp runs in the puck, and I was wrong about what this link forces onto the face.

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